1. Field of the Invention
The invention relates to a power transistor and methods for its fabrication.
2. Description of the Related Art
High-performance power amplifiers and switching devices require low on-resistance, i.e., low resistance during conduction of current by the device, to limit internal power dissipation at high levels of operating current. For low voltage power supply applications, ultra-low on-resistance is essential. Furthermore, inter-electrode capacitance, lead inductance and carrier transit time limit the maximum frequency of operation. Additionally, power devices must efficiently dissipate internally generated heat. With the expanding market for high power communications amplifiers and switching applications (e.g., automotive, mechanical control), there is an increased need for high-performance, low-voltage, inexpensive, solid-state power devices.
Conventional power MOSFETs used in these devices and applications employ planar transistors. Geometries and channel length control required for achieving the desired objectives have been difficult to attain in conventional silicon devices using such planar transistors. A planar transistor has a diffused source electrode and a drain electrode separated by a channel region. A gate electrode overlies the channel region. A gate oxide dielectric separates the channel region from the overlying gate electrode. The planar transistors have relatively large surface area requirements and have developed operational problems in sub-micron integrated circuit geometries, such as leakage currents, isolation, and hot carrier injection.